HT32F0006 32-bit Arm® Cortex®-M0+ Music Synthesizer MCU

The device operates at a frequency of up to 48 MHz with a Flash accelerator to obtain maximum efficiency. It provides up to 128 KB of embedded Flash memory for code/data storage and 16 KB of embedded SRAM memory for system operation and application program usage. A variety of peripherals, such as ADC, 2-channel DAC, I²C, I²S, USART, UART, SPI, QSPI, GPTM, SCTM, CRC-16/32, RTC, WDT, USB2.0 FS, 32-channel music synthesizer, SW-DP (Serial Wire Debug Port), etc., are also implemented in the device. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.

The HT32F0006 integrates Wave Table synthesis function. It can operate up to 32 channels of Wave Table synthesis at one time and control the MIDI Engine to generate melody by setting the special registers. The Wave Table synthesis waveform is stored in external SPI Flash ROM for application flexibility. With these features, it provides enhanced functions and higher performance.

The above features ensure that the device is suitable for use in a wide range of applications, especially in areas such as electronic organs, digital pianos, electronic drums, electric guitars, electric accordions and so on.
 

Music Synthesis Engine (MIDI Engine) – MSE

• Up to 32 simultaneous sounds
• 10-bit Volume Control
• Output sampling frequency up to 50 kHz
• Waveform data lengths of 8, 12 or 16 bits
• Stereo output
• Supports Repeat loop Play
• Supports PDMA interface

Inter-IC Sound (I²S) – I²S

• Master or slave mode
• Mono and stereo
• I²S-justified, Left-justified and Right-justified mode
• 8 / 16 / 24 / 32-bit sample size with 32-bit channel extended
• 8 × 32-bit TX & RX FIFO with PDMA supported
• 8-bit Fractional Clock Divider with rate control
  The I²S is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as ADCs or DACs. The I²S supports a variety of data formats. In addition to the stereo I²S-justified, Left-justified and Right-justified modes, there are mono PCM modes with 8 / 16 / 24 / 32-bit sample size. When the I²S operates in the master mode, then when using the fractional divider, it can provide an accurate sampling frequency output and support the rate control function and fine-tuning of the output frequency to avoid system problems caused by the cumulative frequency error between different devices.

Universal Serial Bus Device Controller -- USB

• Complies with USB 2.0 full-speed (12 Mbps) specification
• On-chip USB full-speed transceiver
• 1 control endpoint (EP0) for control transfer
• 3 single-buffered endpoints for bulk and interrupt transfer
• 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
• 1,024 bytes EP_SRAM used as the endpoint data buffers
  The USB device controller is compliant with the USB 2.0 full-speed specification. There is one control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding registers, which provides maximum flexibility for various applications. The integrated USB full-speed transceiver helps to minimize the overall system complexity and cost. The USB functional block also contains the resume and suspend feature to meet the requirements of low-power consumption.

Debug Support

• Serial Wire Debug Port – SW-DP
• 4 comparators for hardware breakpoint or code / literal patch
• 2 comparators for hardware watch points

Package and Operation Temperature

• 48 pin LQFP (7 mm × 7 mm)
• Operation temperature range: -40°C to +85°C