Supports both 8 bit and 16 bit local CPU interfaces
Compatible with IEEE802.3, 802.3u standards
64-pin LQFP
14KB embedded SRAM for packet buffering
SPI slave interface for MCUs with SPI master for simplifying host interface connection.
Integrates Fast Ethernet MAC/PHY transceiver in one chip
Supports 10Mbps and 100Mbps data rate
Supports full and half duplex operations
Supports 10/100Mbps N-way Auto-negotiation operation
Supports twisted pair crossover detection and auto-correction (Auto-MDIX)
Supports IEEE 802.3x flow control for full-duplex operation
Supports back-pressure flow control for half-duplex operation
Supports Wake-on-LAN function to reduce power by following events
Detection of a change in the network link state
Receipt of a Magic Packet
Receipt of a MS wakeup frame
IPv4/IPv6 checksum offload engine
AX88796C_8051_uIP_Port_v1.0.0_Source.rarAX88796C_Datasheet_V114.pdfAX88796C_Ethernet_Application_DesignNote_v101.pdf